Altium

Design Rule Verification Report

Date: 4/19/2023
Time: 1:18:18 PM
Elapsed Time: 00:00:02
Filename: E:\CEMTREX\ALTIUM PROJECT\USB Audio Amplifer\PCB.PcbDoc
Warnings: 0
Rule Violations: 11

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.254mm) (All),(All) 0
Clearance Constraint (Gap=0.178mm) (InNetClass('SS_DIFF85') OR InNetClass('HS_DIFF90')),(InNet('GND') OR InNet('+1V2') OR InNet('+3V3') OR InNet('+5V') OR InNet('+1V05')) 0
Clearance Constraint (Gap=0.254mm) (InDifferentialPairClass('SS_DIFF85') AND IsVia OR InDifferentialPairClass('HS_DIFF90') AND Isvia),(InDifferentialPairClass('SS_DIFF85') AND IsVia OR InDifferentialPairClass('HS_DIFF90') AND IsVia) 0
Clearance Constraint (Gap=0.5mm) (InNetClass('SS_DIFF85')),(InAnyNet and IsDifferentialPair) 0
Clearance Constraint (Gap=0.203mm) (InNamedPolygon('NONET_L03_P031') OR InNamedPolygon('+1V05_L04_P023')),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 6
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.102mm) (Max=3mm) (Preferred=0.127mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole Size Constraint (Min=0.2mm) (Max=6mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Board Clearance Constraint (Gap=0mm) (All) 5
Matched Lengths(Tolerance=0.203mm) (InDifferentialPairClass('HS_DIFF90')) 0
Matched Lengths(Tolerance=0.051mm) (InDifferentialPairClass('SS_DIFF85')) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 11

Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net VOL_DOWN Between Track (56.434mm,5.538mm)(56.932mm,5.04mm) on Top Layer And Pad S1-2(56.932mm,12.865mm) on Top Layer
Un-Routed Net Constraint: Net +3V3 Between Pad S1-3(61.432mm,4.915mm) on Top Layer And Track (61.468mm,12.901mm)(61.468mm,14.224mm) on Top Layer
Un-Routed Net Constraint: Net VOL_UP Between Track (48.306mm,5.538mm)(48.804mm,5.04mm) on Top Layer And Pad S2-2(48.804mm,12.865mm) on Top Layer
Un-Routed Net Constraint: Net +3V3 Between Pad S3-3(45.43mm,4.915mm) on Top Layer And Pad S2-3(53.304mm,4.915mm) on Top Layer
Un-Routed Net Constraint: Net +3V3 Between Pad S2-3(53.304mm,4.915mm) on Top Layer And Track (53.34mm,12.901mm)(53.34mm,14.224mm) on Top Layer
Un-Routed Net Constraint: Net VOL_MUTE Between Pad S3-1(40.93mm,4.915mm) on Top Layer And Pad S3-2(40.93mm,12.865mm) on Top Layer
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Board Clearance Constraint (Gap=0mm) (All)
Board Outline Clearance(Outline Edge): (Collision < 0.4mm) Between Board Edge And Text "USB AUIDO AMPLIFIER " (58.942mm,22.049mm) on Top Overlay
Board Outline Clearance(Outline Edge): (Collision < 0.4mm) Between Board Edge And Text "V1.1" (62.668mm,20.012mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.126mm < 0.8mm) Between Board Edge And Track (0.226mm,18.144mm)(0.226mm,24.844mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.126mm < 0.8mm) Between Board Edge And Track (0.226mm,18.144mm)(1.126mm,18.144mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.126mm < 0.8mm) Between Board Edge And Track (0.226mm,24.844mm)(5.626mm,24.844mm) on Top Overlay
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